1. Field of the Invention:
The invention relates to the field of interrupt processing in a computer system, and more particular to the field of high-interrupt environments.
2. Art Background:
In a computer system, the processor may be interrupted by other components in the system upon the occurrence of certain events. For example, a network adapter in a computer system may interrupt the processor when a packet of data is received. The network adapter may also interrupt the processor after successfully transmitting a unit of data, so that the processor may free any resources associated with the data (buffers, for example). The processor services the interrupt by reading the received data or freeing the associated resources and then clearing the interrupt. Typically, clearing the interrupt also involves enabling the interrupting device to generate another interrupt, if and when the event re-occurs.
The servicing of interrupts is usually a high priority for the processor. Therefore, when interrupts are generated at a high rate, the processor may become `interrupt bound`. An interrupt bound processor spends most or all of its time servicing interrupts, and as a consequence the processor does not have time to do lower-priority tasks, such as running programs. A processor is likely to become interrupt bound when operating in `high traffic` environments. A high traffic environment is one in which many units (packets) of data are sent and/or received in a short period of time. In high traffic environments, a peripheral device which interrupts the processor every time a packet is received or transmitted may monopolize the processor's time. To prevent monopolization of the processor by an interrupting peripheral device, it is desirable to reduce the number of interrupts associated with sending and receiving data with the peripheral device. However, reducing the number of interrupts must not result in lost data. For example, it is not acceptable to simply ignore interrupts if that means ignoring the data associated with those interrupts.
As mentioned above, network adapters use interrupts to notify the processor when packets (units of data) are received from or transmitted to the network. A typical prior art method used by a network adapter to handle the receipt of packets from a network is as follows:
1) read a packet from the network into the memory of the network adapter; PA1 2) transfer the packet from the memory of the network adapter to the memory of the computer system using Direct Memory Access (DMA); and PA1 3) interrupt the processor to indicate that a packet is ready for processing. PA1 4) temporarily disabling further interrupts from the network adapter to prevent the network adapter from interrupting the processor while the ISR is processing the packet, which prevents re-entrancy problems; PA1 5) resetting the host-side interrupt hardware, which on computer systems using Intel.TM. architecture compatible processors involves sending an end-of-interrupt (EOI) signal to the Programmable Interrupt Controller (PIC) (resetting the host-side interrupt hardware allows for the receipt of another interrupt from the network adapter for another packet, once interrupts for the adapter are re-enabled); PA1 6) processing the received packet, which typically involves reading the packet from the memory (note that if more packets were written to the memory during steps 4 and 5 above, the ISR may for efficiency reasons process the additional packets before returning this has ramifications which are discussed below); PA1 7) re-enabling interrupts from the network adapter; and PA1 8) returning control from the ISR to the software which was being executed before the interrupt occurred, which on systems using Intel architecture processors typically involves the execution of an IRET instruction.
In response to the interrupt in step 3 above, the processor invokes software with instructions to process the received packet. This software is commonly referred to as an interrupt service routine (ISR). The ISR typically performs the following operations:
One problem with the method discussed above occurs when the ISR processes additional packets which were received via DMA or before the ISR received control. After step 5, the processor is ready to receive another interrupt from the network adapter. The writing of the additional packets to the memory using DMA would normally result in an interrupt from the network adapter. However, to prevent re-entrancy into the ISR, interrupts from the network adapter are disabled in step 4 from reaching the processor. Thus, writing the additional packet(s) to memory using DMA results in a `pending` interrupt, which cannot reach the processor until interrupts from the network adapter are reenabled. When interrupts are reenabled at step 7, the network adapter could immediately interrupt the processor, and processing begins at the beginning of the ISR again (step 1). Reentrancy into the ISR is not a problem at this point, because the only processing remaining in the ISR after step 7 is returning from the ISR. However, no packets are available for processing at step 6 because all of the packets in memory were processed during the first invocation of the ISR. As a result of the pending interrupt, time and processor cycles are wasted by invoking the ISR a second time. The increased processing time spent within the ISR increases the probability that the processor will become interrupt bound, especially in high traffic environments.
The amount of processing time consumed by the ISR upon a single invocation increases as the number of packet resources it must process increases. An excessive number of processor cycles should not be spent during execution of the ISR, because other critical processing may need to be performed (other ISRs, for example).
Another problem arises when the network adapter is unable to interrupt the processor immediately. The network adapter may be unable to interrupt the processor immediately if the processor is executing a section of critical software when the network adapter attempts to interrupt. In critical software, interrupts to the processor are disabled and do not reach the processor until the critical software completes and interrupts are reenabled. During this time, one or several packets may be queued. When the ISR is invoked, it may not have time to process all of the packets which have been written into memory via DMA, or the network software may not be able to accept all of the queued packets. To give other software in the system time to execute on the processor, the ISR resets interrupts and returns quickly without processing all of the available packets. As a result, the remaining data packets are `orphaned` until the next interrupt arrives. If no other interrupts arrive, the orphaned packets are lost.
It would be desirable to implement an interrupt processing scheme which addresses the problems discussed above. In particular, the interrupt processing should be adaptable to high traffic environments to reduce the number of interrupts generated in such environments, without a loss of data. Furthermore, the interrupt processing should not result in orphaned data, nor should it require the ISR to consume an excessive number of processor cycles on any single invocation.